A number of memory devices, such as flash memory devices, use analog memory cells to store data Each memory cell stores an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In flash memory devices, for example, each analog memory cell typically stores a certain voltage. The range of possible analog values for each cell is typically divided into threshold regions, with each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired one or more bits.
Single-level cell (SLC) flash memory devices, for example, store one bit per memory cell (or two possible memory states). Multi-level cell (MLC) flash memory devices, on the other hand, store two or more bits per memory cell (i.e., each cell has four or more programmable states). In multi-level NAND flash memory devices, for example, floating gate devices are employed with programmable threshold voltages in a range that is divided into multiple intervals with each interval corresponding to a different multibit value. To program a given multibit value into a memory cell, the threshold voltage of the floating gate device in the memory cell is programmed into the threshold voltage interval that corresponds to the value.
The analog values stored in memory cells are often distorted. The distortions are typically due to, for example, back pattern dependency (BPD), noise and intercell interference (ICI) and read disturb. For a more detailed discussion of distortion in flash memory devices, see, for example, J. D. Lee et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, 264-266 (May 2002) or Ki-Tae Park, et al., “A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories,” IEEE J. of Solid State Circuits, Vol. 43 No. 4, 919-928, (April 2008), each incorporated by reference herein.
ICI is a consequence of parasitic capacitances between cells and is generally considered to be the one of the most prominent sources of distortion. Id. For example, ICI is known to increase with technology scaling and becomes a significant source of distortion of the threshold voltage distribution as transistor sizes become smaller. Thus, ICI is of particular concern for reliable MLC memories, as ICI limits the number of voltage levels that can reliably be stored in the MLC memory.
A number of techniques have been proposed or suggested for mitigating the effect of noise, ICI and other disturbances in flash memory devices. While these existing methods have helped to improve the decoding performance of flash memory devices, they suffer from a number of limitations, which if overcome, could further improve the reliability of flash memory devices. For example, current flash memory devices typically only use hard data from the flash memory, or consider only data read from a single page for detection. It is well known, however, that soft data can improve error rate performance in the decoding process. Also, considering data from multiple pages or wordlines can improve error rate performance.
Thus, a need exists for multi-tier detection and decoding techniques that feature multiple error recovery steps where advanced error recovery steps use soft data from the flash memory device or data from additional pages or wordlines. A need also exists for multi-tier detection and decoding and multi-tier error recovery techniques where data is recovered with low delay. As used herein, the terms “multi-tier detection and decoding” and “multi-tier error recovery” are used interchangeably.